Embodiments of the disclosed technology relate to an array substrate, a liquid crystal display and a method of manufacturing the array substrate.
Currently, liquid crystal displays are commonly used flat panel displays; thin film transistor liquid crystal displays (TFT-LCDs) have become the main type of liquid crystal displays due to advantages of low volume, low power consumption, no irradiation and so on. Generally, a TFT-LCD comprises a liquid crystal panel, a driving circuit and a backlight. The liquid crystal panel is the main component of the TFT-LCD and comprises an array substrate, a color filter substrate and a liquid crystal layer filled between the array substrate and the color filter substrate. The liquid crystal molecules of the liquid crystal layer rotate in order under the control of the voltages provided by the driving circuit so as to produce switch of light between brightness and darkness, and the control of the voltage is accomplished by thin film transistors.
FIG. 1A is a partial structure top view of a conventional array substrate, and FIG. 1B is a sectional structural side view along a line A-A in FIG. 1A. As shown in FIGS. 1A and 1B, the array substrate comprises: a base substrate 1; data lines 5 and gate lines 2, formed to transversely and longitudinally cross each other on the base substrate 1; pixel units, arranged in a matrix form and defined by the data lines 5 and the gate lines 2. Each pixel unit comprises a thin film transistor (TFT) switch and a pixel electrode 11. Each TFT switch comprises a gate electrode 3, a source electrode 7, a drain electrode 8, and an active layer 6, which comprises a semiconductor layer 601 and an ohmic contact layer 602. The gate electrode 3 is connected with a gate line 2; the source electrode 7 is connected with a data line 5; the drain electrode 8 is connected with the pixel electrode 11, and the active layer 6 is formed between the source and drain electrodes 7 and 8 and the gate electrode 3. The gate line 2 and the gate electrode 3 are both covered by a gate insulation layer 4 so as to make the gate line 2 and the gate electrode 3 insulated from the TFT switch and the data line 5. The TFT switch and the data line 5 are both covered by a passivation layer 9 insulating the TFT switch and the data line 5 from the pixel electrode 11. The pixel electrode 11 can be connected with the drain electrode 8 through a passivation layer via 10. The above structure and patterns constitute a pixel region 30 on the array substrate (the portion surrounded by the dotted line in FIG. 1A), and an interface region 40 is outside of the pixel region. The detailed pattern in the interface region 40 is not shown in FIG. 1A.
As the development of TFT-LCD technologies, the requirement on viewing angle property of TFT-LCDs is continuously improved, so the technologies for wide viewing angle are proposed. Among the technologies for wide viewing angle, a technology of fringe field switch (FFS) adopts a transparent pixel electrode and a transparent common electrode both formed on a base substrate to produce a fringe field between the transparent common electrode and the transparent pixel electrode to drive the liquid crystal molecules above the transparent common electrode and the transparent pixel electrode. This FFS technology can widen viewing angles and improve the transmitting efficiency of the liquid crystal layer, thus has become a wide viewing angle technology which is widely researched and used.
The array substrate of an FFS type TFT-LCD can generally be manufactured by a five-mask process: in a first mask process, a first transparent common electrode layer (e.g., an indium tin oxide (ITO) layer) is formed on the base substrate, and then patterned to form a transparent common electrode comprising a common electrode line and a transparent electrode; gate lines and gate electrodes are formed in a second mask process, that is, the gate lines and the gate electrodes are formed on the transparent common electrode; patterns (SDT patterns) comprising data lines and active layers (generally comprising a semiconductor layer and an active silicon island), source and drain electrodes of TFTs are formed in a third gray tone or half tone mask, wherein the source and drain electrodes are formed above the active layer in each TFT, and the data lines are formed perpendicular to the gate lines; a passivation layer and passivation layer via holes are formed in a fourth mask, wherein the passivation layer is formed on the source and drain electrodes and cover the entire base substrate, and the passivation layer via holes are formed at the positions corresponding to the drain electrodes; in the fifth mask, a transparent pixel electrode layer (e.g., an ITO layer) is formed and then patterned to form the transparent pixel electrodes connected with the drain electrodes through the passivation layer via holes.
It is important to reduce the number of the mask process during the manufacturing of a TFT-LCD for lowering the manufacturing cost of TFT-LCDs. Thus, in order to reduce the manufacturing cost of TFT-LCDs a four-mask process is currently adopted to manufacture FFS type TFT-LCDs. The four-mask process differs from the five-mask process in that: the transparent common electrode, gate lines and gate electrodes are simultaneously formed in the first mask process by using a gray tone or half tone mask; at the same time, peripheral driving circuits, such as an interface region of the gate lines, an interface region of the common electrodes and so on, are also formed in the first mask process.
However, in the conventional technology, in forming the transparent common electrode, the gate lines and the gate electrodes through a gray tone or half tone mask, since the concentration of developing solution in the pixel region adjacent to the driving circuit pattern in the peripheral driving circuit region become not uniform with respect to the driving circuit pattern, which causes the thickness of the photoresist in the pixel region adjacent to the diving circuit pattern layer after exposure and development is obviously smaller than that in the other portions of the pixel region. In the resultant product, there exists a cloudy Mura (as shown in FIG. 2A) at the edge of the pixel region adjacent to the driving circuit pattern. Such cloudy Mura may have an influence on the subsequent etching procedure, causing increased difficulty for the etching process, making it difficult to control the parameters of the etching process, giving rise to occurrence of etching Mura, and decreasing the yield of products.